The present invention relates to a semiconductor device having a protected area, and a layout design system.
Moisture entry or the like from a dicing surface of a semiconductor device (hereinafter, may be called a semiconductor chip) may adversely affect circuit elements and a wiring layer on a semiconductor chip. Such moisture entry frequently occurs on a semiconductor chip including an interlayer insulating layer made of a low-dielectric constant insulating material. Furthermore, the circuit elements and wiring on the semiconductor chip may be broken by cracks appearing on the interlayer insulating layer during dicing or resin molding on the semiconductor chip.
Japanese Unexamined Patent Publication No. 2006-210648 discloses a semiconductor device that includes an element formation area overlying a semiconductor substrate and a seal ring area formed around the element formation area. The seal ring area includes a wiring layer having wiring and a via layer having rows of slit vias.
As is disclosed in Japanese Unexamined Patent Publication No. 2006-210648, a typical seal ring area formed around an element formation area as a protected area of the element formation area includes multiple seal rings including slit vias and wiring layers. The multiple seal rings can suppress moisture entry into the element formation area and the occurrence of cracks on an interlayer insulating layer with higher reliability.
The multiple seal rings each have multiple bridge patterns formed perpendicularly to the extending direction of the slit via and the wiring layer. Like the seal ring, the bridge pattern is configured by slit vias and a wiring layer. The slit vias and the wiring layer of the bridge pattern couple the slit vias and the wiring layer of the seal ring. The slit vias and the wiring layer are opposed to each other inside and outside of the seal ring. The seal rings coupled by the bridge patterns increase the mechanical strength of the seal ring area.